This invention relates generally to CMOS semiconductor integrated circuits and more particularly, it relates to improved CMOS clamp circuits for limiting the voltage rise or drop on a particular node.
As is generally well known in CMOS digital integrated circuits normal logic levels are (1) a low or "0" logic state which is represented by a lower power supply potential VSS and (2) a high or "1" logic state which is represented by an upper power supply potential VCC. The lower power potential VSS is usually connected to an external ground or 0 volts and upper potential VCC is typically connected to a voltage source referenced above ground, i.e., +5.0 volts. It is often desirable to limit the voltage swings of CMOS circuits so as to improve their performance. By so limiting the voltage swing at a particular node, less charge will be required to be charged up and discharged at a particular node in a given circuit, thereby permitting a faster speed of operation.
While clamp circuits in CMOS technology are usually adequate to perform the function of limiting the voltage, they suffer from the disadvantage of consuming quiescent power. Thus, the problems of excessive power dissipation have limited the use of clamp circuits to critical areas of the design. Ideally, CMOS technology due to the complementary structure is generally considered to be a low power technology since standard logic circuits consume virtually no quiescent power and consumes power only during switching. However, this is true only if the voltage on the clamped node is at a true logic state of VSS or VCC. Typically, the clamp circuit by itself does not dissipate excess power but results in power consumption of circuits whose gate logic is connected to the clamp circuit. In practice, when the clamped node is not at one of the true logic states the logic gates connected thereto will not be completely turned off. If the actual logic voltages are above the (VSS + V.sub.Tn) voltage level or below the (VCC-V.sub.Tp) voltage level, then some amount of quiescent power will be dissipated. V.sub.Tn and V.sub.Tp are the respective body-effect enhanced thresholds of an N-channel transistor and a P-channel transistor.
All of the prior art clamp circuits in CMOS technology have generally resulted in an excessive amount of power being consumed when used to limit the voltage swings. Therefore, it would be desirable to provide improved CMOS clamp circuits which consume less power than has been traditionally available. Further, it would be expedient to provide CMOS clamp circuits which include a power down mode of operation in which the clamping transistor is deactivated, thereby reducing power consumption.
SUMMARY OF THE INVENTION
According, it is a general object of the present invention to provide improved CMOS clamp circuits which consume less power than has been traditionally available.
It is an object of the present invention to provide an improved CMOS clamp circuit which is formed of a sense inverter, an N-channel MOS clamping transistor, and a P-channel MOS clamping transistor.
It is another object of the present invention to provide an improved CMOS clamp circuit which includes a power-down mode of operation in which the clamping transistor is deactivated, thereby further reducing power consumption when the output of the sense inverter is not being used.
It is still another object of the present invention to provide an improved CMOS clamp circuit which includes a sense inverter, an N-channel MOS clamping transistor, a P-channel MOS clamping transistor, an enabling transistor, and a power-down transistor.
In one embodiment of the present invention, there is provided an improved CMOS clamp circuit which includes a sense inverter having an input node for receiving a sense current signal and an output node for generating a voltage output, an N-channel MOS clamping transistor, and a P-channel MOS clamping transistor. The N-channel transistor has its drain connected to an upper power supply potential and its source connected to the input node of the inverter. The P-channel transistor has its drain connected to a lower power supply potential and its source connected to the input node of the inverter. The gates of the N-channel and P-channel transistors are connected to the output node of the inverter.
In another embodiment of the present invention, there is provided an improved CMOS clamp circuit which further includes a P-channel MOS enabling transistor and an N-channel MOS pull-down transistor. In still another embodiment, there is provided an improved CMOS clamp circuit which further includes an N-channel MOS enabling transistor and a P-channel MOS pull-up transistor.